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Crystal-to-HSTL 100MHz / 200MHz PCI ExpressTM Clock Synthesizer
General Description
The ICS842S104 is a PLL-based clock generator specifically designed for PCI ExpressTM Clock Generation 2 applications. This device generates either a 200MHz or 100MHz differential HSTL clock from an input reference of 25MHz. The input reference may be derived from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference is applied to the XTAL_IN pin with the XTAL_OUT pin left floating.The device offers spread spectrum clock output for reduced EMI applications. An I2C bus interface is used to enable or disable spread spectrum operation as well as select either a down spread value of -0.35% or -0.5%.The ICS842S104 is available in a lead-free 24-Lead package.
ICS842S104
DATA SHEET
Features
* * * * * * * * * * *
Four differential HSTL output pairs Crystal oscillator interface: 25MHz Output frequency: 100MHz or 200MHz RMS phase jitter @ 200MHz (12kHz - 20MHz): 1.27ps (typical) Cycle-to-cycle jitter: 25ps (maximum) I2C support with readback capabilities up to 400kHz Spread Spectrum for electromagnetic interference (EMI) reduction 3.3V core/1.5V to 2.0V output operating supply 0C to 70C ambient operating temperature Available lead-free (RoHS 6) package PCI Express Gen2 Jitter Compliant
HiPerClockSTM
Block Diagram
XTAL_IN XTAL_OUT SDATA SCLK
Pullup Pullup 25MHz
Pin Assignment
PLL Divider Network
4 4
OSC
SRCT[1:4] SRCC[1:4]
I2 C Logic
SRCT3 SRCC3 VSS VDDO SRCT2 SRCC2 SRCT1 SRCC1 VSS VDD VSS nc
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
SRCC4 SRCT4 VDDO SDATA SCLK XTAL_OUT XTAL_IN VDD VSS nc VDDA VSS
ICS842S104 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View
ICS842S104CG REVISION A MARCH 17, 2010
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Table 1. Pin Descriptions
Number 1, 2 3, 9, 11, 13, 16 4, 22 5, 6 7, 8 10, 17 12, 15 14 18, 19 20 21 23, 24 Name SRCT3, SRCC3 VSS VDDO SRCT2, SRCC2 SRCT1, SRCC1 VDD nc VDDA XTAL_IN, XTAL_OUT SCLK SDATA SRCT4, SRCC4 Type Output Power Power Output Output Power Unused Power Input Input I/O Output Pullup Pullup Description Differential output pair. HSTL interface levels. Power supply ground. Output power supply pins. Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. Core supply pins. No connect. Analog supply for PLL. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. I2C compatible SCLK. This pin has an internal pullup resistor. LVCMOS/LVTTL interface levels. I2C compatible SDATA. This pin has an internal pullup resistor. LVCMOS/LVTTL interface levels. Differential output pair. HSTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLUP Parameter Input Capacitance Input Pullup Resistor Test Conditions Minimum Typical 2 51 Maximum Units pF k
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal I2C serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the serial interface initialize to their default setting upon power-up, and therefore, use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3A. The block write and block read protocol is outlined in Table 3B, while Table 3C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h).
Table 3A.Command Code Definition
Bit 7 6:5 4:0 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation. Chip select address, set to "00" to access device. Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be "00000".
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Table 3B. Block Read and Block Write Protocol
Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 Description = Block Write Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte/Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 Description = Block Read Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte Count from slave - 8 bits Acknowledge Data Byte 1 from slave - 8 bits Acknowledge Data Byte 2 from slave - 8 bits Acknowledge Data Bytes from Slave/Acknowledge Data Byte N from slave - 8 bits Not Acknowledge
Table 3C. Byte Read and Byte Write Protocol
Bit 1 2:8 9 10 11:18 19 20:27 28 29 Description = Byte Write Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Data Byte - 8 bits Acknowledge from slave Stop Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39 Description = Byte Read Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Data from slave - 8 bits Not Acknowledge Stop
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Control Registers
Table 3D. Byte 0: Control Register 0
Bit 7 6 @Pup 0 1 Name Reserved SRC[T/C]4 Description Reserved SRC[T/C]4 Output Enable 0 = Disable (Hi-Z) 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Hi-Z) 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Hi-Z) 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z) 1 = Enable Reserved Reserved Reserved
Table 3G. Byte 3:Control Register 3
Bit 7 6 5 4 3 2 1 0 @Pup 1 0 1 0 1 1 1 1 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
5
1
SRC[T/C]3
4
1
SRC[T/C]2
3 2 1 0
1 1 0 0
SRC[T/C]1 Reserved Reserved Reserved
Table 3H. Byte 4: Control Register 4
Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 1 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Table 3E. Byte 1: Control Register 1
Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Table 3I. Byte 5: Control Register 5
Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Table 3F. Byte 2: Control Register 2
Bit 7 6 5 4 3 @Pup 1 1 1 0 1 Name SRCT/C Reserved Reserved Reserved Reserved Description Spread Spectrum Selection 0 = -0.35%, 1 = -0.5% Reserved Reserved Reserved Reserved SRC Spread Spectrum Enable 0 = Spread Off, 1 = Spread On Reserved Output Frequency Control 0 = 100MHz 1 = 200MHz 5
2
0
SRC
1 0
1 1
Reserved FOUTCTL
ICS842S104CG REVISION A MARCH 17, 2010
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Table 3J. Byte 6: Control Register 6
Bit 7 @Pup 0 Name TEST_SEL Description REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N TEST Clock Mode Entry Control 0 = Normal Operation, 1 = REF/N or Hi-Z Mode Reserved Reserved Reserved Reserved Reserved Reserved
Table 3K. Byte 7: Control Register 7
Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 1 Name Description Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0
6
0
TEST_MODE
5 4 3 2 1 0
0 1 0 0 1 1
Reserved Reserved Reserved Reserved Reserved Reserved
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI XTAL_IN Other Inputs Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V 0V to VDD -0.5V to VDD + 0.5V 50mA 100mA 77.5C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, VDDO = 1.5V to 2.0V, TA = 0C to 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD - 0.21 1.5 Typical 3.3 3.3 Maximum 3.465 VDD 2.0 106 21 7 Units V V V mA mA mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, TA = 0C to 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current SDATA, SCLK SDATA, SCLK VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 10 Units V V A A
Table 4C. HSTL DC Characteristics, VDD = 3.3V 5%, VDDO = 1.5V to 2.0V, TA = 0C to 70C
Symbol VOH VOL VOX VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Crossover Voltage; NOTE 2 Peak-to-Peak Output Voltage Swing Test Conditions Minimum 0.9 0 40% x (VOH - VOL) + VOL 0.6 Typical Maximum 1.2 0.4 65% x (VOH - VOL) + VOL 1.1 Units V V % V
NOTE 1: Outputs terminated with 50 to GND. NOTE 2: Defined with respect to output voltage swing at a given condition. ICS842S104CG REVISION A MARCH 17, 2010 7 (c)2010 Integrated Device Technology, Inc.
ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Table 5. Crystal Characteristics
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pF parallel resonant crystal. Test Conditions Minimum Typical Fundamental 25 50 7 MHz pF Maximum Units
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = 3.3V 5%, TA = 0C to 70C
Symbol fMAX fref Parameter Output Frequency Reference frequency = 200MHz, 25MHz crystal input tREFCLK_HF_RMS Phase Jitter RMS; NOTE 1, 2 High Band: 1.5MHz - Nyquist (clock frequency/2) = 200MHz, 25MHz crystal input Low Band: 10kHz - 1.5MHz tsk(o) tjit(O) tjit(cc) tL odc Output Skew; NOTE 2, 3 Phase Jitter, RMS (Random) Cycle-to-Cycle Jitter PLL Lock Time Output Duty Cycle 48 200MHz, Integration Range: 12kHz - 20MHz PLL Mode 1.27 25 60 52 50 ps ps ps ms % 0.95 ps Test Conditions FOUTCTL = 0 FOUTCTL = 1 Minimum Typical 100 200 25 Maximum Units MHz MHz
tREFCLK_LF_RMS
Phase Jitter RMS; NOTE 1
0.31
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for tREFCLK_HF_RMS (High Band) and 3.0 ps RMS for tREFCLK_LF_RMS (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Typical Phase Noise at 200MHz
Noise Power
dBc Hz
Offset Frequency (Hz)
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Parameter Measurement Information
3.3V5% 1.5V to 2.0V 3.3V5%
Phase Noise Plot Noise Power
VDD VDDO
Qx
SCOPE
Phase Noise Mask
VDDA
HSTL
nQx
GND
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
0V
3.3V HSTL Output Load AC Test Circuit
RMS Phase Jitter
SRCC(1:4) SRCC(1:4) SRCT(1:4) SRCT(1:4)
t PW
t tcycle n
tcycle n+1
PERIOD
tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles
Cycle-to-Cycle Jitter
ICS842S104CG REVISION A MARCH 17, 2010
odc =
t PW t PERIOD
x 100%
Output Duty Cycle/Pulse Width/Period
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS842S104 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V VCC .01F VCCA .01F 10F 10
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins Inputs:
LVCMOS Control Pins
All control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
Outputs:
HSTL Outputs
All unused HSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Crystal Input Interface
The ICS842S104 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_IN C1 18pF X1 18pF Parallel Crystal XTAL_OUT C2 18pF
Figure 2. Crystal Input Interface
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition,
3.3V 3.3V R1 100 Ro ~ 7 Ohm RS Driv er_LVCMOS 43 Zo = 50 Ohm C1 XTAL_IN R2 100 0.1uF XTAL_OUT
matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal.
Cry stal Input Interf ace
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC=3.3V Zo = 50 Ohm C1 XTAL_IN R1 50 0.1uF XTAL_OUT
Zo = 50 Ohm LVPECL R2 50
Cry stal Input Interf ace
R3 50
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Termination for HSTL Outputs
VDDO VDD
Zo = 50 + Zo = 50 HSTL R1 50 R2 50 HSTL
ICS HiPerClockS HSTL Driv er
Figure 4. HSTL Output Termination
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Schematic Example
Figure 5 shows an example of ICS842S104 application schematic. In this example, the device is operated at VDD = 3.3V and VDDO = 1.8V. Both input options are shown. The device can either be driven using a quartz crystal or a 3.3V LVCMOS signal. The C1 and C2 = 18pF are recommended for frequency accuracy. For different board layouts, the C1 and C2 may be slightly adjusted for optimizing fequency accuracy. The LVHSTL output driver termination examples are shown in this schematic. The decoupling capacitor should be located as close as possible to the power pin.
Logic Control Input Examples
VDD
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 Not Install
VDD
VDDO
SRCT1 SRCC1
Zo = 50 Ohm +
Zo = 50 Ohm
-
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
12 11 10 9 8 7 6 5 4 3 2 1
nc VSS VD D VSS SR C C 1 SR C T 1 SR C C 2 SR C T 2 VD D O VSS SR C C 3 SR C T 3
U1
R1 50
R2 50
VDD=3.3V
VSS VD D A nc VSS VD D XTAL_IN XTAL_OU T SC LK SD ATA VD D O SR C T 4 SR C C 4
VDDO=1.8V
13 14 15 16 17 18 19 20 21 22 23 24
VDD R3 10
SRCT4 VDDA C3 10uF C4 0.01u VDD VDDO SRCC4
Zo = 50 Ohm +
Zo = 50 Ohm
-
VDD
25MHz C2 18pF
X1 1 8 p F R4 50 R5 50
C1 18pF R6 SP R7 SP
SC LK SD AT A
VDD
VDDO
J1 5 SDA 4 3 2 SCL 1
R8
0
(U1-10)
VDD
(U1-17)
(U1-4)
VDDO
(U1-22)
R9
0
C5 0.1uF
C6 0.1uF
C7 0.1uF
C8 0.1uF
Figure 5. ICS842S104 Schematic Example
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
PCI Express Application Note
PCI Express jitter analysis methodology models the system response to reference clock jitter. The below block diagram shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link.
In the jitter analysis, the Tx and Rx serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is:
t ( s ) = H3 ( s ) x [ H1 ( s ) - H2 ( s
The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is:
s) = X ( s ) x H3 ( s ) x [ H1 ( s ) - H2(
In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz to 50MHz) and the jitter result is reported in peak-peak. For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz - Nyquist (High Band). The below plots show the individual transfer functions as well as the overall transfer function Ht. The respective -3 dB pole frequencies for each transfer function are labeled as F1 for transfer function H1, F2 for H2, and F3 for H3. For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements.
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Magnitude of Transfer Functions - PCIe Gen 1 0
F1: 2.2e+007 F2: 1.5e+006 F3: 1.5e+006
-10
-20 Mag (dB)
-30
-40 H1 H2 H3 Ht=(H1-H2)*H3 10
4
-50
-60 3 10
10 10 Frequency (Hz)
5
6
10
7
PCIe Gen 1 Magnitude of Transfer Function
Magnitude of Transfer Functions - PCIe Gen 2A 0
Magnitude of Transfer Functions - PCIe Gen 2B 0
F1: 1.6e+007 F2: 5.0e+006 F3: 1.0e+006
F1: 1.6e+007 F2: 8.0e+006 F3: 1.0e+006
-10
-10
-20 Mag (dB)
-20 Mag (dB)
-30
-30
-40 H1 H2 H3 Ht=(H1-H2)*H3 10
4
-40 H1 H2 H3 Ht=(H1-H2)*H3 10
4
-50
-50
-60 3 10
10 10 Frequency (Hz)
5
6
10
7
-60 3 10
10 10 Frequency (Hz)
5
6
10
7
PCIe Gen 2A Magnitude of Transfer Function
PCIe Gen 2B Magnitude of Transfer Function
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS842S104. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS842S104 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * The maximum current at 70C is as follows: IDD_MAX = 101.7mA IDDA_MAX = 19.4mA Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (101.7mA + 19.4mA) = 419.6mW Power (outputs)MAX = 32mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 32mW = 128mW
* *
Total Power_MAX (3.465V, with all outputs switching) = 419.6mW + 128mW = 547.6mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 77.5C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.548W * 77.5C/W = 112.5C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
Table 7. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 77.5C/W 1 73.2C/W 2.5 71.0C/W
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the HSTL output pair. HSTL output driver circuit and termination are shown in Figure 6.
VDDO
Q1
VOUT
RL 50
Figure 6. HSTL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (VOH_MAX /RL) * (VDD_MAX - VOH_MAX) Pd_L = (VOL_MAX /RL) * (VDD_MAX - VOL_MAX) Pd_H = (1.2V/50) * (2.0V - 1.2V) = 19.2mW Pd_L = (0.4V/50) * (2.0V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
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ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Reliability Information
Table 8. JA vs. Air Flow Table for a 24 Lead TSSOP
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 77.5C/W 1 73.2C/W 2.5 71.0C/W
Transistor Count
The transistor count for ICS842S104 is: 11,891
Package Outline and Package Dimensions
Package Outline - G Suffix for 24 Lead TSSOP Table 9. Package Dimensions
All Dimensions in Millimeters Symbol Minimum Maximum N 24 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153
ICS842S104CG REVISION A MARCH 17, 2010
19
(c)2010 Integrated Device Technology, Inc.
ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
Ordering Information
Table 10. Ordering Information
Part/Order Number 842S104CGLF 842S104CGLFT Marking ICS842S104CGL ICS842S104CGL Package "Lead-Free" 24 Lead TSSOP "Lead-Free" 24 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature 0C to 70C 0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
ICS842S104CG REVISION A MARCH 17, 2010
20
(c)2010 Integrated Device Technology, Inc.
ICS842S104 Data Sheet
CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESSTM CLOCK SYNTHESIZER
6024 Silver Creek Valley Road San Jose, California 95138
Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT
Technical Support netcom@idt.com +480-763-2056
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.

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